1. Field of the Invention
The present invention concerns a charge transfer memory as well as a method for the fabrication of this memory.
It can be applied notably to photosensitive matrices used in video systems. In this type of application, the charges stored in the memory come from photosensitive elements. The invention more particularly concerns the transfer of charges stored in shift registers to a reading register.
2. Description of the Prior Art
Charge transfer memories, whether used to record charges coming from photosensitive elements or to record charges generated by any other means, generally have, in a known way, a succession of charge transfer shift registers in which the stored charges are transferred towards one of ends, called the final end, of each of these registers, to be transferred a reading register which itself works as a charge transfer shift register. The charges thus transferred from the shift registers to the reading register are read at the end of this reading register by a measuring amplifier.
The shift registers used in this memory are parallel to a first direction. These registers are generally of the type with "four phases and two levels of integration of electrodes or of polycrystalline silicon". The reading register is parallel to a second direction which is perpendicular to the first direction. As shall be seen in detail further below, this register is, in the case of the invention, is of the type with "two phases and three levels of polycrystalline silicon".
FIG. 1 gives a schematic view, in perspective, of a charge transfer memory having, in a known way, shift registers and a reading register with transfer of charges.
The shift registers are designated by the references 1, 2, 3, 4 and the reading register is designated by reference 5. The number of shift registers has been limited to four to make it easier to represent them. These shift registers are parallel to a first direction Y while the reading register 5 is parallel to a second direction X which is itself preferably perpendicular to the first direction Y.
The shift registers and the reading register are made on a semiconductor substrate 6, with a first type (P type for example) of doping, which supports a semiconductor layer 7 with a second type of doping (N type for example). An insulating layer 8 covers the semiconductor layer 7.
Parallel to the axis Y, each shift register has successive groups of electrodes. Only one group of four electrodes 9 has been shown as an example for the register 1. It is clear that this register has other groups identical to the group 9, aligned with it in the direction Y. Each of these groups has four electrodes, 11, 12, 13 and 14, for the transfer and storage of charges. These electrodes are arranged in series and are in contact with the insulating layer 8. They enable the charges to flow, in a known way, in a pre-determined direction indicated by the arrow 15, by means of transfer potentials and potential wells which appear beneath the electrodes of each group at the interface between the semiconductor layer 7 and the insulating layer 8 when the cyclical voltages, V.sub.1, V.sub.2, V.sub.3, V.sub.4, are respectively applied to the four electrodes of each group. These voltages respectively have different phases and equal extreme values. The charges are thus transmitted from one group to another, in the direction of the arrow 15, to be brought to one end of each shift register which ends with a final transfer electrode 16. This final electrode is carried to a cyclical potential having, for example, the same phase and the same extreme values as the voltage V.sub.1 applied to the first electrode 11 of the group.
The reading register 5 has, along the second axis X, for each shift register, and to make the charges always flow in one and the same direction, as defined by the arrow 17, a pair of reading electrodes in contact with the insulating layer 8.
Each of the pairs of reading electrodes has, for example, for the shift register 2, in order to transfer the charges stored beneath the final electrode 19 of this register, a storage electrode 18, called a reading electrode, contiguous to the final electrode 19 of the shift register 2 considered, and a transfer electrode 20, called a reading electrode, contiguous to the reading storage electrode 18. This transfer electrode is also contiguous to a reading storage electrode 21, corresponding to the final electrode 16 of the adjacent shift register 1, in the sequence of registers and in the direction 17 of the transfer of charges in the reading register.
In a known way, the pairs of successive electrodes 20, 21 and 18, 23 of reading register 5 are respectively powered by cyclical voltages VL1, VL2 which are in phase opposition and have the same extreme values.
FIG. 2 gives a schematic sectional view XOY of the memory of FIG. 1. The structure of this memory is shown herein in greater detail and as in the prior art. The same references are repeated for the same elements in this figure and in FIG. 1.
This FIG. 2 again shows the semiconductor layer 7, with a second type of doping (N type for example), the insulating layer 8 and, on this insulating layer, certain electrodes of the reading register 5 and certain electrodes of the shift register 1. Thus, there are shown, the electrodes 11, 12, 13, 14 of this shift register 1 to which there are applied the phase-shifted voltages V1, V2, V3, V4. This figure also shows the final electrode 16 of this shift register, to which there is applied the voltage VF, the storage electrode 21 of the reading register 5, the transfer electrode 22 which is contiguous to this storage electrode 21, as well as the next storage electrode 25. This figure also shows other transfer electrodes 26, 27, 28 and other storage electrodes 29, 30, 31 of the reading register. The pairs of electrodes such as 21, 22, 25, 26,.. of the reading register are supplied with the voltages VL1, VL2 mentioned further above.
Semiconductor zones with a third type of doping (N type for example), shown at 32, 33, 34 and 35 in the figure, are made facing the transfer electrodes 22, 26, 27, 28, . . . of the reading register.
Charges coming from the shift registers flow in this reading register by means of potential wells and transfer potentials that appear beneath the successive pairs, such as 22-25,. . ., of electrodes of the reading register.
FIG. 3 is a graph of the potentials V which appear at the interface between the semiconductor layer 7 and the insulating layer 8, when the above-mentioned potentials are applied to the electrodes of the shift register and to the electrodes of the reading register. For each of the phases .phi.1, .phi.2 of the voltages VL1, VL2 applied, the successive pairs of electrodes of the reading register, these potentials show potential wells P1, P2, P3 with a depth VA, and transfer potential "landings" or stages with values VB, VC, VD.
These wells and transfer potentials enable the charges to be conveyed into the reading register in the direction of the arrow 17 for example. These charges come from a potential well P4 of the shift register. In this shift register, these charges are conveyed to the ends of each shift register through the application of the potentials V1, V2, V3, V4 to the different electrodes, and through the application of the potential VF to the final electrode 16 of this register (VF=V1).
The transfer potential, of the level VC, resulting from the application of the potential VF to the final electrode 16 of the shift register, has a higher level than the transfer potential VD resulting from the application of the potential VL1 to the electrode 21.
The result thereof is that the charges (electrons in the example considered) are normally transferred from the potential well P4, present beneath the storage electrode 14 of the shift register, to the potential well PO, present beneath the storage electrode 21 of the reading register. The transfer potential VC created by the voltage VF applied to the final electrode 16 is the same as the one which creates the potential well PO during the transfer, and electrons present in the well P1 of the reading register can return to the well P4 of the shift register (it must be noted that the axis V of the voltages points downwards). In fact, once the reading register is charged, the voltage VF remains in the low state and the potentials VL1 and VL2 are controlled between the low and high levels in order to remove the charges to the reading register output (arrow 17 in FIG. 1). It is during this shift that the charges can rise again towards the shift register.
The fact that charges flowing in the reading register might return to a shift register is a very serious drawback in this type of prior art register.